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Xilinx Virtex-7 FPGA VC707 Evaluation Kit

Xilinx Virtex-7 FPGA VC707 Evaluation Kit

UPGRADE YOUR BROWSERWe have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you! ‎09-03-2012 02:20 AM I want to ask some questions about PLL_ADV  in spartan-6, my design include a PLL_ADV,  when I configuration it according to  the reference design xapp879, all inputs of PLL_ADV are the same as the reference design ,but the feedback signal DO is different. I don't know why, and I don't know whether the DO is effect the outputs of PLL_ADV?   thanks    ‎09-03-2012 08:55 AM ‎09-03-2012 06:35 PM      ‎09-03-2012 06:41 PM



UPGRADE YOUR BROWSERWe have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!   By K R Ranjith and Deepak Shankar, Mirabilis Design   The Zynq SoC’s unique combination of a dual-core ARM Cortex-A9 MPCore processor, many embedded peripherals and I/O controllers, and programmable logic makes application task partitioning between the software-driven processor cores and the programmable logic a major challenge. System-architecture decisions that are difficult to make without dynamic exploration include the selection of tasks requiring hardware acceleration, use of the Zynq SoC’s local memory as cache or exclusively for use by the programmable logic, memory bandwidth allocation, and the design of communications between the ARM processor and the programmable logic. We at Mirabilis Design have developed a virtual platform for the Zynq-7000 Programmable SoC to help you answer these complex questions.   This platform, called VisualSim, is a heterogeneous modeling, simulation and ysis environment that uses a combination of cycle- and timing-accurate models for simulating the performance and power consumption of the Zynq SoC’s internal components. You can use the VisualSim platform for early architecture exploration. VisualSim uses state-based dynamic power measurement during the simulation, which allows you to architect applications with power in mind.   The following examples of an HD video-processing application use a mix of software and programmable logic. We used the following methodology to develop the HD video application:   Instantiate the Zynq-7000 platform component Set up the use case in terms of arrival rate and data priority Define system behavior in terms of task flow and state machines Define the following characteristics of each task: priority, execution time, instruction list, number of variables, and number of pixels processed at one time Run the system simulation by varying parameters including the hardware attributes (such as clock speed), system attributes (such as the mapping of the behavior task to processor and logic), and task attributes (such as priority and timing). yze the output reports for timing, power, bandwidth, and resource utilization Modify the attributes and rerun the simulation to find system bottlenecks and to fully validate the specification     The proposed HD video platform must process at least 10K macro blocks in 20 msec. System power should not exceed 3W. The system architecture must be defined to meet these requirements. We simulated two different system designs:   All tasks running on the ARM Cortex-A9 MPCore processor Applications distributed between the ARM Cortex-A9 MPCore processor and hardware accelerators built using programmable logic   We used the pre-configured and customizable VisualSim Xilinx Zynq-7000 All Programmable SoC platform, shown in Figure 1 below, for these experiments. This platform consists of hardware architectural elements such as the dual-core ARM Cortex-A9 processor; SDRAM and Flash memory controllers; DMA controllers; peripherals and I/O controllers including CAN, Ethernet, and USB; hardware timers; and a generous chunk of Xilinx 7-series FPGA. The VisualSim Zynq-7000 Simulation Environment generates performance ysis reports including application latency, device throughput, processor performance, and system-level power consumption (average power, instant power and battery consumption).       Figure 1: VisualSim Zynq 7000 Programmable SoC Template     In the above figure, we defined the HD video application as a task-flow diagram. Figure 2 shows the “Behavior Flows” hierarchical block in detail.  In addition to the HD Video application itself, the system design includes additional housekeeping tasks defined as background processes. Figure 2 also shows a parameters block with the attributes of the Video Post-Processing task.       Figure 2: VisualSim Zynq 7000 User Application Behavior Flow     Each blue behavior block in Figure 2 represents a specific application task. Each behavior block includes a parameters list (data size, priority, destination processing resource, and task name). VisualSim allows you to easily modify task mapping during architecture exploration. You can map tasks to either the Zynq SoC’s processor or to programmable logic to achieve the desired performance and power consumption. VisualSim executes a task’s actual instruction sequence or a synthetic generated trace to accurately emulate task execution on the ARM Cortex-A9 MPCore processor.   You use the VisualSim Power Modeling Toolkit to model system power consumption. The Power Modeling toolkit enables designers and architects to capture dynamic power of the entire system in a model. This feature allows you to trade off performance and power using a single architectural model. Each standard device or component model can have as many as four power states—standby (leakage), idle, active, and wait—and a transition cycle time. There can be as many as twelve power states defined for the Zynq SoC’s programmable logic. When the operation state of a device changes (idle, standby, wait, and busy), the power level goes to the new state. There is a delay to go to the new state called a transition cycle that improves simulation accuracy.   We constructed the HD video application’s behavior task model and hardware mapping in 10 man-hours and then ran the simulation on a 2.6GHz Microsoft Windows 10 platform with 4GBytes of RAM. VisualSim simulated 800μsec of system time using 46 seconds of wall-clock time.   System ysis focused on three aspects: system attribute settings, mapping of tasks to processor and programmable logic, and power management.  We considered two use cases to explore system performance and power consumption:   Run all application tasks on the Zynq SoC’s dual-core ARM Cortex-A9 MPCore processor alone Distribute the applications to the Zynq SoC’s ARM processor and programmable logic     Case 1: Run Applications on the dual-core ARM Cortex-A9 MPCore processor   For the initial design exploration, we mapped all of the image-processing tasks onto the Zynq SoC’s dual-core ARM cortex A9 MPCore processor as shown in Figure 3.       Figure 3: Mapping of the HD Video behavior onto the dual-core ARM Cortex-A9 MPCore processor     We set the target destination of the behavior task blocks in Figure 2 to “any_core,” instructing VisualSim to map tasks to either Core 1 or Core 2. The system dispatcher, which is part of the operating system, then makes the final allocation decision at run time.   Simulation results generated include average power consumption of the complete system, the number of processed macro blocks, individual resource power consumption, and task latency. A plot of the average power consumption appears in Figure 4 and a text display with task latency information appears in Figure 5.   Figure 4: System Average Power Consumption and Number of Macro Block Processing         Figure 5: Task Latency Reports     Simulation results show that the power consumption is less than 3W when all applications are mapped onto the Zynq SoC’s dual-core ARM Cortex-A9 MPCore processor, meeting our power-consumption goal, however the performance is inadequate. The design goal is to process 10K macro blocks but only 1643 macro blocks were processed in the allotted 20msec. From the hardware platform statistics, we can see that the “Rotate_Frame” task consumes the most CPU cycles so accelerating this task using programmable logic is a likely step towards achieving the performance goal.     Case 2: Distributing the HD video tasks to the Zynq SoC’s ARM processor and programmable logic   In this case, we moved the “Rotate_Frame” task to a hardware accelerator constructed from the Zynq SoC’s programmable logic. We use basic VisualSim modeling libraries to model the accelerator, as shown in Figure 6.       Figure 6: Hardware accelerator using the Zynq SoC’s programmable logic     First, we modeled the hardware accelerator using the VisualSim Zynq 7000 Platform as shown in Figure 6.  Then we simply changed the mapping parameters of the “Rotate_Frame” task to use the hardware accelerator by modifying the “Select_Partitioning” parameter from “SW” to “HW” as shown in Figure 7.       Figure 7: Rotate_Frame task mapping set to programmable logic     The reports of average system power consumption and number of macro blocks processed for Case 2 appear in Figure 8.   Figure 8: Average Power Consumption and Number of Macro Block Processing     The average system power consumption plot shows that the power consumption now slightly exceeds the 3W goal but performance has improved significantly, to 11700 macro blocks, which exceeds our 10K goal. Looking at the instantaneous power consumption plot generated for the Rotate_Frame hardware accelerator, shown in Figure 9, we see that the hardware accelerator logic is always active. We can lower the accelerator’s power consumption by gating the power using a finite state machine.       Figure 9: Instantaneous Power Consumption of Image Rotate Function       The results after introducing gated power appears in Figure 10:       Figure 10: Average system power consumption instantaneous power of Rotate_Frame Function     Introducing power gating reduces performance by 6% but still meets our performance requirement of processing 10K macro blocks in the allotted time while the total system power consumption is now 2.6W, well below our 3W power goal.   In our studies, we found that stall-time, cache-hit-ratio, and task-latency reports helped us determine the behavior tasks best targeted for hardware acceleration. Also, the block-level power information provided visibility into management algorithms that can be deployed to reduce total power consumption. None of this ysis would have been possible with a prototyping board but it is easily handled by the VisualSim platform.    By K R Ranjith and Deepak Shankar, Mirabilis Design The Zynq SoC’s unique combination of a dual-core ARM Cortex-A9 MPCore processor, many embedded peripherals and I/O controllers, and programmable logic makes application task partitioning between the software-driven processor cores and the programmable logic a major challenge. System-architecture decisions that are difficult to make without dynamic exploration include the selection of tasks requiring hardware acceleration, use of the Zynq SoC’s local memory as cache or exclusively for use by the programmable logic, memory bandwidth allocation, and the design of communications between the ARM processor and the programmable logic. We at Mirabilis Design have developed a virtual platform for the Zynq-7000 Programmable SoC to help you answer these complex questions. This platform, called VisualSim, is a heterogeneous modeling, simulation and ysis environment that uses a combination of cycle- and timing-accurate models for simulating the performance and power consumption of the Zynq SoC’s internal components. You can use the VisualSim platform for early architecture exploration. VisualSim uses state-based dynamic power measurement during the simulation, which allows you to architect applications with power in mind. The following examples of an HD video-processing application use a mix of software and programmable logic. We used the following methodology to develop the HD video application:   The proposed HD video platform must process at least 10K macro blocks in 20 msec. System power should not exceed 3W. The system architecture must be defined to meet these requirements. We simulated two different system designs:  We used the pre-configured and customizable VisualSim Xilinx Zynq-7000 All Programmable SoC platform, shown in Figure 1 below, for these experiments. This platform consists of hardware architectural elements such as the dual-core ARM Cortex-A9 processor; SDRAM and Flash memory controllers; DMA controllers; peripherals and I/O controllers including CAN, Ethernet, and USB; hardware timers; and a generous chunk of Xilinx 7-series FPGA. The VisualSim Zynq-7000 Simulation Environment generates performance ysis reports including application latency, device throughput, processor performance, and system-level power consumption (average power, instant power and battery consumption).   Figure 1: VisualSim Zynq 7000 Programmable SoC Template  In the above figure, we defined the HD video application as a task-flow diagram. Figure 2 shows the “Behavior Flows” hierarchical block in detail.  In addition to the HD Video application itself, the system design includes additional housekeeping tasks defined as background processes. Figure 2 also shows a parameters block with the attributes of the Video Post-Processing task.   Figure 2: VisualSim Zynq 7000 User Application Behavior Flow  Each blue behavior block in Figure 2 represents a specific application task. Each behavior block includes a parameters list (data size, priority, destination processing resource, and task name). VisualSim allows you to easily modify task mapping during architecture exploration. You can map tasks to either the Zynq SoC’s processor or to programmable logic to achieve the desired performance and power consumption. VisualSim executes a task’s actual instruction sequence or a synthetic generated trace to accurately emulate task execution on the ARM Cortex-A9 MPCore processor. You use the VisualSim Power Modeling Toolkit to model system power consumption. The Power Modeling toolkit enables designers and architects to capture dynamic power of the entire system in a model. This feature allows you to trade off performance and power using a single architectural model. Each standard device or component model can have as many as four power states—standby (leakage), idle, active, and wait—and a transition cycle time. There can be as many as twelve power states defined for the Zynq SoC’s programmable logic. When the operation state of a device changes (idle, standby, wait, and busy), the power level goes to the new state. There is a delay to go to the new state called a transition cycle that improves simulation accuracy. We constructed the HD video application’s behavior task model and hardware mapping in 10 man-hours and then ran the simulation on a 2.6GHz Microsoft Windows 10 platform with 4GBytes of RAM. VisualSim simulated 800μsec of system time using 46 seconds of wall-clock time. System ysis focused on three aspects: system attribute settings, mapping of tasks to processor and programmable logic, and power management.  We considered two use cases to explore system performance and power consumption:    For the initial design exploration, we mapped all of the image-processing tasks onto the Zynq SoC’s dual-core ARM cortex A9 MPCore processor as shown in Figure 3.   Figure 3: Mapping of the HD Video behavior onto the dual-core ARM Cortex-A9 MPCore processor  We set the target destination of the behavior task blocks in Figure 2 to “any_core,” instructing VisualSim to map tasks to either Core 1 or Core 2. The system dispatcher, which is part of the operating system, then makes the final allocation decision at run time. Simulation results generated include average power consumption of the complete system, the number of processed macro blocks, individual resource power consumption, and task latency. A plot of the average power consumption appears in Figure 4 and a text display with task latency information appears in Figure 5. Figure 4: System Average Power Consumption and Number of Macro Block Processing    Figure 5: Task Latency Reports  Simulation results show that the power consumption is less than 3W when all applications are mapped onto the Zynq SoC’s dual-core ARM Cortex-A9 MPCore processor, meeting our power-consumption goal, however the performance is inadequate. The design goal is to process 10K macro blocks but only 1643 macro blocks were processed in the allotted 20msec. From the hardware platform statistics, we can see that the “Rotate_Frame” task consumes the most CPU cycles so accelerating this task using programmable logic is a likely step towards achieving the performance goal.   In this case, we moved the “Rotate_Frame” task to a hardware accelerator constructed from the Zynq SoC’s programmable logic. We use basic VisualSim modeling libraries to model the accelerator, as shown in Figure 6.   Figure 6: Hardware accelerator using the Zynq SoC’s programmable logic  First, we modeled the hardware accelerator using the VisualSim Zynq 7000 Platform as shown in Figure 6.  Then we simply changed the mapping parameters of the “Rotate_Frame” task to use the hardware accelerator by modifying the “Select_Partitioning” parameter from “SW” to “HW” as shown in Figure 7.   Figure 7: Rotate_Frame task mapping set to programmable logic  The reports of average system power consumption and number of macro blocks processed for Case 2 appear in Figure 8. Figure 8: Average Power Consumption and Number of Macro Block Processing  The average system power consumption plot shows that the power consumption now slightly exceeds the 3W goal but performance has improved significantly, to 11700 macro blocks, which exceeds our 10K goal. Looking at the instantaneous power consumption plot generated for the Rotate_Frame hardware accelerator, shown in Figure 9, we see that the hardware accelerator logic is always active. We can lower the accelerator’s power consumption by gating the power using a finite state machine.   Figure 9: Instantaneous Power Consumption of Image Rotate Function   The results after introducing gated power appears in Figure 10:   Figure 10: Average system power consumption instantaneous power of Rotate_Frame Function  Introducing power gating reduces performance by 6% but still meets our performance requirement of processing 10K macro blocks in the allotted time while the total system power consumption is now 2.6W, well below our 3W power goal. In our studies, we found that stall-time, cache-hit-ratio, and task-latency reports helped us determine the behavior tasks best targeted for hardware acceleration. Also, the block-level power information provided visibility into management algorithms that can be deployed to reduce total power consumption. None of this ysis would have been possible with a prototyping board but it is easily handled by the VisualSim platform. You must be a registered user to add a comment. If you've already registered, sign in. Otherwise, register and sign in.





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