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Spartan-3E Starter Kit Board User Guide                 Chapter 1: Introduction and OverviewChapter 2: Switches, Buttons, and KnobChapter 3: Clock SourcesChapter 4: FPGA Configuration OptionsChapter 5: Character LCD ScreenChapter 6: VGA Display PortChapter 7: RS-232 Serial PortsChapter 8: PS/2 Mouse/Keyboard PortChapter 9: Digital to og Converter (DAC)Chapter 10: og Capture CircuitChapter 11: Intel StrataFlash Parallel NOR Flash PROMChapter 12: SPI Serial FlashChapter 13: DDR SDRAMChapter 14: 10/100 Ethernet Physical Layer InterfaceChapter 15: Expansion ConnectorsChapter 16: XC2C64A CoolRunner-II CPLDChapter 17: DS2432 1-Wire SHA-1 EEPROM                       Chapter 1Introduction and Overview Spartan-3ESpartan-3ESpartan-3ECoolRunner-IIXilinx : Spartan-3E (50XC3S500E-4FG320C), CoolRunner™-II (XC2C64A-5VQ44C)Platform Flash (XCF04S-VO20C)50 MHz: 128 Mbit Flash, 16 Mbit SPI Flash, 64 MByte DDR SDRAM: 10/100 Phy, JTAG USB,涓や釜9RS-232, PS/2/, , ,LED, , 100hirose6: VGA16 - 2 LCDLinear Technologies TPS75003IC: , /, , : 32RISCXilinxMicroBlaze PicoBlazeDDREthernetI/O Choose the Starter Kit Board for Your Needs Spartan-3E FPGA Features and Embedded Processing FunctionsSpartan3-E FPGA Spartan3-E FPGASpartan3-ENOR FlashNOR Flash PROM FPGAMicroBlaze™ 32-bit RISCPicoBlaze™ 8-bit DDRLearning Xilinx FPGA, CPLD, and ISE Development Software Basics Spartan3-E FPGA FPGACPLDISE Advanced Spartan-3 Generation Development BoardsMicroBlaze™ 32-bit EDKFPGASP-305Key Components and Features1)XC3S500E(Spartan-3e)232I/O320FPGA1000024MbitFlash PROM364XC2C64A CoolRunner CPLD464 MByte (512 Mbit) of DDR SDRAM, 16 , 100+ MHz516 MByte (128 Mbit) of NOR Flash (Intel StrataFlash)FPGAMicroBlaze/616 Mbits of SPI serial Flash (STMicro)FPGAMicroBlaze/7162LCD8PS/29VGA10)10/100浠ュおPHYFPGAMAC1129RS232DTEDCE12FPGA/CPLD/USB1350Hz141SHA-1EEPROM15Hirose FX2163174SPI-DAC182SPIADC19ChipScope™20218LED22423424SMA258Design Trade-OffsConfiguration Methods Galore!FPGASpartan-3E3Spartan-3EJTAGUSBJTAGXILINX USBVoltages for all ApplicationsTITPS75003Spartan-3EFPGAFPGADDR SDRAMUSBJTAG1.8V  Chapter 2Switches, Buttons, and Knob   Slide SwitchesLocations and Labels42.1  Operation    FPGA3.3VFPGA2msFPGAUCF Location Constraints图2.2为4UCFI/OI/OPush-Button SwitchesLocations and Labels42.3BTN_NORTHBTN_EASTBTN_SOUTHand BTN_WEST a BTN_*b FPGABTN_SOUTHOperationFPGA3.3v2.4FPGA2.5UCFBTN_SOUTHFPGA UCF Location Constraints图2.5为4UCFI/OI/ORotary Push-Button SwitchLocations and Labels2.3432ROT_AROT_BROT_CENTEROperation2Push-Button SwitchFPGA3.3V2.62.9UCFRotary Shaft Encoder2.7FGPA2.9UCFFPGAAB2.8     UCF Location ConstraintsDiscrete LEDsLocations and Labels8LED   OperationLED390Spartan-3ELED UCF Location Constraints Chapter 3: Clock SourcesOverview图3.13150MHz2) SMAFPGASMA38-DIPClock Connections    Bank0I/O3.1DCMVoltage ControlFPGAI/O Bank0JP9JP9JP93.3v3.3VJP9为2.5V  50 MHz On-Board Oscillator50MHz40502500Hz50ppm Auxiliary Clock Oscillator Socket     FPGA50MHz8FPGADCM50MHz SMA Clock Input or Output ConnectorSMAFGPASMAUCF ConstraintsLocationClock Period Constraints Chapter 4FPGA Configuration Options FPGAJTAGUSBFPGAUSB-JTAGPlatform Flash PROM Xilinx XC2C64A CPLD4 Mbit Xilinx XCF04S serial Platform Flash PROMPlatform Flash PROMFPGA16 Mbit ST Microelectronics SPI serial Flash PROMSPISPI serial Flash PROMFPGA128 Mbit Intel StrataFlash parallel NOR Flash PROMBPI UpBPI DownStrataFlash parallel NOR Flash PROMFPGASpartan-3E FPGA’s MultiBoot FPGA图4.1USB/4.2PROGFPGAFPGADONELED 4 Mbit Xilinx Platform Flash PROM为FPGAJTAGPlatform Flash PROMFPGABPI UpBPI DownMultiBootStrataFlash parallel Flash PROMFPGA64-macrocell XC2C64A CoolRunner II CPLDCPLD   Configuration Mode Jumpers4.1J30FPGA PROG Push Button    PROGFPGAFPGADONE Pin LED    FPGADONELEDProgramming the FPGA, CPLD, or Platform Flash PROM via USB4.1USBBUSBUSBiMPACTFPGA Platform Flash PROMCPLDFlash PROM Connecting the USB CableUSB A/B4.3A PCBWindowsLEDUSB Programming via iMPACTiMPACTUSBFPGAFPGAUSBProject Navigator Configure Device (iMPACT)4.5    iMPACTJTAG4.6FPGAAssign New Configuration File4.6FPGACCLKiMPACT4.7JTAGiMPACT TCK JTAGFPGAFGPAProgramIMPACTUSB IMPACTFPGAIMPACT4.9FPGADONE Programming Platform Flash PROM via USBUSB-JTAGXilinx XCF04S serial Platform Flash PROMPROMFPGAPROMFPGAPROMFPGACCLKFPGACCLK1.5MHzPROMCCLKFPGAXilinx XCF04S Platform Flash25 MHzCCLK4.104.114.12 Generating the PROM File4.13IMPACTPROM File Formatter4.144.154.164.174.18    PROMIMPACTPROM4.19PROMOperation/Generate File4.20IMPACTPROM4.21Programming the Platform Flash PROMUSBJTAGPROMPlatform Flash PROM4.224.254.26Erase Before ProgramingPlatform Flash PROMVerifyPROMLoad FPGAPlatform Flash PROMFPGAFPGA4.1OK IMPACTLoad FPGAPROG_BFPGAPlatform Flash PROMFPGADONE LED    Chapter 5Character LCD Screen Overview    216LCDLCD8XILINXFPGA4LCD5.1LCDASCII50MHzPicoBlaze  Character LCD Interface Signals5.1LCDVoltage CompatibilityLCD5VFPGAI/O3.3VFPGALCDLCD5V TTLFPGA3.3VLCMOS5V TTL390LCDFPGASrtataFlsah I/OLCD_RWLCDLCDInteraction with Intel StrataFlash    5.14LCDStrataFlash SF_D<11:8>5.2LCD/StrataFlash SF_CE0=1,FPGA/LCDLCDLCD_RW=0,FPGA/   StrataFlash 8SF_BYTE=0FPGA/LCDSF_D<15:8>UCF Location ConstraintsLCD Controller    216LCDSitronix ST7066USamsung S6A0069X or KS0066U Hitachi HD44780SMOS SED1278Memory Map1DD RAMRAMDD RAMDD RAMDD RAMCG ROMCG RAM图5.3320X000X0F0X400X4FDD RAM80400X100X270X500X67DD RAMDD RAM DD RAMCG RAM DD RAMDD RAM CG RAMDD RAMDD RAM112) CG ROMROMCG ROMLCD5.4DD RAM CG ROM0X5316DD RAMS0X53DB[7:4]=0101DB[3:0]=00115.4S/CG ROMASCIIROMASCII8CG RAM8DD RAM 0X000X07    3CG RAMRAM(CG RAM)8855.5CG RAMCG RAM CG RAMCG RAM DD RAMCG RAM CG RAM DD RAMCG RAM11图5.5CG RAMDD RAM0x03CG RAMCG RAMCG RAM DD RAM10580     Command Set5.3LCD482421)  LCD_ELCD2   ASCII/ANSI0x20DD RAM DD RAM0X000I/D1   82us1.64ms3DD RAM5.3DD RAM0X000   40us1.6ms 440usCG RAMDD RAMCG RAM DD RAM DD RAMCG RAM11.1)  /40us    52)  DD RAM DD RAM 1640   40us3)  0X2840us7CG RAM璁剧疆CG RAMCG RAM40us8DD RAM 璁剧疆DD RAMDD RAM40us9)BFBF1BF0CG RAMDD RAMCG RAMDD RAM1us10CG RAMDD RAMDD RAM DD RAMCGRAM CGRAM1140us11CG RAMDD RAMDD RAM DD RAMCGRAM CG RAM1140us OperationFour-Bit Data Interface4LCD5.6LCD50MHz T=20nsDF_D<11:8>LCD_RS/LCD_RWLCD_E40ns230ns1250MHzLCD_RWFPGA Transferring 8-Bit Data over the 4-Bit Interface    8248241us5.6840us1.64msInitializing the Display8位PicoBlaze PicoBlaze 1)  FPGALCD4A15msFPGA50MHz15ms750000BSF_D<11:8>=0x3LCD_E12C4.1ms50MHz205000DSF_D<11:8>=0x3LCD_E12E100us50MHz5000FSF_D<11:8>=0x3LCD_E12G40us50MHz2000HSF_D<11:8>=0x2LCD_E12I40us50MHz20002)   4A0x28B0X06C/0x0cD1.64ms82000Writing Data to the DisplayDD RAMDD RAM75.3CG RAM DD RAM8CG ROMCG RAM5.4CG ROM CG RAM581DD RAM Disabling the Unused LCD   FPGALCDLCD_ELCD_RWLCD   Chapter 6VGA Display Port DB15VGAPCLCD6.1VGAFPGA5VGAVGA_REDVGA_BLUEVGA_GREEN75VGA0V0.7VVGA_HSYNCVGA_VSYNCLVTTLLVCMOS3I/OVGA_REDVGA_BLUEVGA_GREEN86.1VGAVESAVGAFPGA640480VGASignal Timing for a 60 Hz, 640x480 VGA DisplayVGACRTLCDCRTLCDCRTCRTLCDCRT6.2VGAVGATTL36.16.2VGAHS(VS)VS60120Hz VGA Signal Timing 6.264048025Mhz60Hz卤16.3TPWTFPTBP)VGA      HSHS1VSDDR SDRAM HSVSRAMUCF Location Constraints图6.4VGAUCFI/OI/O                    Chapter 7RS-232 Serial Ports Overview图7.12RS-232DB9 DCEDTEDCEPCDTERS-232DCE图7.1FPGA2DB9FPGALVTTLLVCMOSMaxim RS-232Maxim LVTTLRS-232FGPAMaximFPGARXDDCDDTRDSR7.1RTSCTS UCF Location Constraints图7.27.3 RS-232DTEDCEUCFI/OI/O   Chapter 8PS/2 Mouse/Keyboard Port   PS/2/6DINJ148.1PS/28.115FPGAPC2PS/2PS/2118.28.2PS/28.21PCKeyboard2PS/2PS/28.3100msF0SHIFE0E0 F08.3  1108LSB12030KHz118.2Mouse   111108LSB13301122010213218.42030KHz   PS/28.5XYXSYS1   XYXVYV13350ms   LR1Voltage Supply   5V5V8.1UCF Location Constraints   Chapter 9Digital to og Converter (DAC)SPI4DACDACLTC2624124J5Digilent 6SPI Communication图9.2FPGASPIDACSPI4FPGASPI_SCKSPI_MOSIDACSPI_MISO   Interface Signals9.1FPGA DAC SPI_MOSISPI_MISOSPI_SCKSPIDAC_CSDACDAC_CLRDACDACDACSPI Disable Other Devices on the SPI Bus to Avoid ContentionSPIFPGADAC9.2StrataFlash PROMSPI_MISO SPI Communication Details9.3SPISPI_SCK50MHzLTC2624DAC_CSFPGASPI_MOSIMSBLTC2624SPI_SCKSPI_MOSI4nsLTC2624SPI_SCKSPI_MISOFPGASPI_SCKFPGADAC_CSSPI_SCKSPI_MISO3132FPGASPIDAC_CSDACCommunication Protocol图9.4LTC2624 DACDAC243232D/ASPI3232DAC32DACFPGA84COMMAND[3:0]=0011DACFPGA4FPGA12DAC432Specifying the DAC Output Voltage    9.2DAC12D[110]FPGASPIDAC9.1VREFERENCE4AB3.3VCD2.5V5DAC Outputs A and B    9.2DACAB3.5V卤5DAC Outputs C and D   9.3DACCD2.5V卤5 UCF Location Constraints     Chapter 10: og Capture Circuit DAC10.1LTC6912-1J710.2LTC1407A-1 ADCADCFPGA  Digital Outputs from og InputsVINAVINB14D[13:0]10.1GAINVINAVINB10.2ADC1.65V10.21.65VVINAVINBADC1.25V1.65V1.25VADC1421428192  Programmable Pre-AmplifierLTC6912-12VINAVINBDAC1.65 Interface10.1FPGASPI_MOSISPI_MISOSPI_SCKSPIAMP_CSProgrammable Gain   10.2J7VINAVINB1.65V   110010.2SPI Control Interface图10.3SPI824B3AMP_DOUTFPGAAMP_CSSPI10.4SPI_SCKSPI_MOSISPI_SCKAMP_DOUT10MHz  UCF Location Constraints og to Digital Converter (ADC)    LTC1407A-1ADCAD_CONVInterface   10.3FPGAADCSPI_MOSISPI_MISOSPI_SCKSPIDACDAC_CSDAC_CLR SPI Control Interface图10.6SPIADCAD_CONVADCAD_CONV1.5MHzADC142     图10.7AD_CONVSPIADCSPI_MISOSPI_SCKADCSPI10.634ADC142 UCF Location ConstraintsDisable Other Devices on the SPI Bus to Avoid ContentionSPIFPGAAMP ADC10.4StrataFlash PROMSPI_MISOFPGAPlatform Flash PROM Connecting og Inputs   DCACVINAVINB     Chapter 11Intel StrataFlash Parallel NOR Flash PROM 11.1128Mbit16MbyteIntel StrataFlash parallel NOR Flash PROMStrataFlashStrataFlash PROM1FPGA2FPGASpartan-3E FPGA’s MultiBoot3MicroBlaze4MicroBlazeDDR4FPGAStrataFlash Connections11.1FPGAStrataFlashXC3S500E FPGA2MbitFPGA-to-StrataFlash256MbitStrataFlash128MbitSF_A24StrataFlashXC3S500E8BPIFPGA 4StrataFlashXC2C64 CPLD11.1StrataFlash     Shared Connections    StrataFlashStrataFlashCharacter LCDLCD4StrataFlash PROMSF_D<11:8>11.2FPGASF_CE0LCD_RWStrataFlash PROMLCDXilinx XC2C64A CPLDXilinx XC2C64A CoolRunner CPLDStrataFlash5SF_A<24:20>BPI4A<23:20>FPGA4I/OStrataFlash PROMSF_A<23:0>16CPLD16 Mbyte StrataFlash PROMSF_A<24>StrataFlash PROMSF_A<24>FX2FX2_IO<32>SPI Data LineSF_D<0>SPISPI_MISOPlatform Flash PROM11.3 FPGAUCF Location ConstraintsAddress图11.2StrataFlashUCF Data图11.3UCFControl图11.4UCFSetting the FPGA Mode Select PinsFPGABPI UP BPI DOWN11.4                         Chapter 12SPI Serial FlashSTMicroelectronics M25P16 16 Mbit SPI serial FlashSPI FlashFPGASpartan-3E FPGA 12.1SPI Flash1) 2IP3MicroBlazeDDR SDRAMUCF Location Constraints图12.2SPI Flash PROMUCFConfiguring from SPI FlashSPI Flash FPGASPI Flash Setting the FPGA Mode Select PinsSPIFPGA12.412.3Creating an SPI Serial Flash PROM FileFPGASPI Serial Flash PROMSetting the Configuration Clock RateM25P16 SPI serial FlashFPGA12MHz12.5Formatting an SPI Flash PROM File12.6IMPATCPROM File Formatter12.712.812.912.1012.11PROMIMPACTPROMPROM12.12XCF04S Platform Flash PROMPROM12.1312.14IMPACTPROM12.8PROM FormatterMySPIFlash.mcsDownloading the Design to SPI FlashSPI Flash1XAPP445XSPIJTAGSPI Flash2)SPI FlashPicoBlazeHyperlinkPCSPI FlashFPGAPicoBlazeSPI serial Flash3JTAGFPGA JTAGSPI FlashFPGA4ISE8.2iDownloading the SPI Flash using XSPIXSPISPI FlashDownload and Install the XSPI Programming UtilityXSPIXAPP445Attach a JTAG Parallel Programming CableXSPIJTAGXilinx Parallel Cable IVDigilent JTAG3 USBUSBIMPACTJTAGJ1212.15aJ1212.3J12SPI FlashJTAGJTAG3J12JTAG3J1112.15b12.2INITInsert Jumper on JP8 and Hold PROG_B LowJTAGSPI FlashFPGAFPGAJP8PROGFPGAPROG_B12.16Programming the SPI Flash with the XSPI SoftwareDOSXSPIXSPIXAPP445xspiSPI-formatted Flash SPI FlashSPI FlashM12P16 SPI FlashFlashC:\xspi>xspi -spi_dev m25p16 -spi_epv -mcs -i MySPIFlash.mcs -o output.txt Enter112.17SPI FlashJP812.16aFPGASPI Flash PROMDONE LEDAdditional Design Details图12.18SPI Flash12.1Spartan-3EShared SPI Bus with PeripheralsSPI FlashSPISPI12.18SPI FlashFPGAPCI12.3Other SPI Flash Control SignalsM25P16 SPI FlashWVariant Select Pins, VS[2:0]SPIFPGAVS[20]SPISPI FlashM25P16 FlashVS[20]111VS[20]3.3VBPIVS[20]FlashA[19:17]StrataFlash parallel Flash PROMSPIVS[20]I/OStrataFlash parallel Flash PROMSPI FlashFGPAJumper Block J11SPIFPGACSO_BSPI FlashCSO_BJ11SPI FlashSPI_ALT_CS_JP11J11SPI FlashJP12SPI FlashJ11Programming Header J1212.15J12JTAGSPI FlashMulti-Package LayoutSTMicroelectronicsM25Pxx SPIFlash16Mbit12.198-lead, 8x6 mm MLP8-pin SOIC 16-pin SOIC8-pin SOIC1MLP16-pin SOIC19016-pin SOIC41SPI Flash PROMSPI Flash SPI Flash FPGA2FPGAPROMSpartan-3E FPGA’s FG320XC3S500EXC3S1200EXC3S1600E FPGASPI FlashPROMFPGASPI Flash3SPI FlashChapter 13DDR SDRAM16512 Mbit (32M x 16) Micron Technology DDR SDRAM  (MT46V32M16)13.1 DDR SDRAM FPGA’s I/O Bank 3 I/O Bank 3 DDR SDRAM 2.5V5VLTC34121.25V2.5VFPGA DDR SDRAMDDR SDRAMSD_CK_PFPGA I/O Bank 0B9FPGA’s Digital Clock Managers (DCMs)MicroBlaze OPB DDREDK 8.1i MicroBlaze OPB DDR SDRAM IP DDR SDRAM Connections13.1FPGADDR SDRAMUCF Location ConstraintsAddress图13.2DDR SDRAMUCFData 图13.3DDR SDRAMUCFControl图13.4DDR SDRAMUCFReserve FPGA VREF Pins图13.5I/O Bank 3 VREFI/O                         Chapter 1410/100 Ethernet Physical Layer InterfaceLAN83C185 10/100PHYRJ-4514.1FPGAMAC25M Ethernet PHY ConnectionsFPGAMIILAN83C185 Ethernet PHY14.214.1 MicroBlaze Ethernet IP CoresPHYMicroBlaze MACEDKMACOPBMACOPB65MHz100Mbps6.5MHz10MbpsUCF Location Constraints    图14.410/100 Ethernet PHY interfaceUCFI/O     Chapter 15Expansion ConnectorsI/O1100hiroseFPGA43I/O15LVDS I/O226    3Agilent or TektronixHirose 100-pin FX2 Edge Connector (J3)    10015.1FX2-100P-1.27DS Hirose1.27mmFX2图15.243FPGAI/OFX25I/O5FX2_IP<38:35>FX2_IP<40>15.1FX2I/OFX2        Voltage Supplies to the Connector100hirose FX15.25.0V5VFPGA0I/OHirose FPGA I/O 00I/O3.3VJP92.5VFPGAI/ORSDSLVDS2.5VFX2 BConnector Pinout and FPGA Connections15.1100hirose FXFPGAFX225015.115.18位LED36-J1J2J4J6 Compatible BoardSpartan-3EFX2DigilentVDEC1 Video Decoder Board Mating Receptacle ConnectorsHirose FX2-100P-1.27DS100Differential I/OFX2J315I/OLVDSRSDS I/O15.2I/ODIFF_TERMUsing Differential InputsLVDSRSDS15.3a10015.2FPGAFX2151615.3bSpartan-3EI/ODIFF_TERMI/O120I/O1516图15.415.515.2Using Differential OutputsLVDSRSDSI/O Bank 02.5VI/O Bank 03.3V2.5VFX2JP92.5VUCF Location Constraints图15.7FX2UCFSix-Pin Accessory Headers6Digilent Peripheral ModulesI/OHeader J115.86J16904FPGAFX2_IO<4:1>J1FX2J13.3VHeader J215.96J26904FPGAFX2_IO<8:5>J2FX2J23.3VHeader J415.10J4J10.164FPGAFX2_IO<12:9>J4FX2J43.3VUCF Location Constraints图15.11UCFConnectorless Debugging Port Landing Pads (J6)15.1J6AgilentAgilent’s FPGAXilinx ChipScope ProFPGA EditorAgilent TektronixChipScope Pro15.318FPGA18FX2J36J1J2J4            Chapter 16XC2C64A CoolRunner-II CPLD     Xilinx XC2C64A CoolRunner-II CPLDCPLDCPLDFPGAXilinx Platform Flash PROMIntel StrataFlash PROMCPLD1FPGAFPGA_M<2:0>=000XCF04S Platform Flash PROMPlatform Flash PROMCPLDFPGA2BPI-UPFPGA_M<2:0>=010FPGAStrataFlash PROM 5 A[24:20] 00000BPI-DOWNFPGA_M<2:0>=011FPGAStrataFlash PROM 5 A[24:20]11111BPIFPGADONEA[24:20]为ZZZZZBPI5FPGACPLDBPICPLDCPLDI/O132158璺崇嚎JP10WDT_ENCPLD XC_WDT_ENXC_PROG_BCPLDFPGAPROG_BStrataFlash PROMSF_A<24>FX2FX2_IO<32>16MStrataFlash PROM24SF_A<23:0>SF_A<24>StrataFlash PROM   UCF Location Constraints FPGA Connections to CPLDCPLD        Chapter 17DS2432 1-Wire SHA-1 EEPROM    SHA-1Maxim DS2432EEPROM17.1DS2432 EEPROMMaxim1-Wire1-Wire/ SHA-1(MAC)   DS2432 EEPROMFPGAXilinxXAPP780UCF Location Constraints     





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